Areas of Teaching Interest
VLSI Design, Topics in VLSI Design, Computer Architecture, Topics in Computer Architecture
Areas of Research Interest
Energy Efficient Computing, Energy Efficient Circuits and Systems, Low Power VLSI Systems, Power Aware Cloud Computing, Power-Aware and Secure Systems, Computer Architecture and Benchmarking.
Ph.D, Pennsylvania State University
- S. Mostafa and E. John, “Reducing Power and Cycle Requirement for Fast Fourier Transform of Electrocardiogram Signals Through Low Level Arithmetic Optimizations for Cardiac Implantable Devices”, Journal of Low Power Electronics, Volume 12, Number 1, March 2016, pp. 21-29(9).
- S. Koppa, and E. John “Leakage Current Compensation in Switched Capacitor Circuits for Implantable Cardiac Devices”, The 2nd International Conference on Biomedical Engineering and Sciences (BIOENG'16), Las Vegas, NV, July 25 – 28, 2016.
- S. Mostafa and E. John “Performance and Energy Evaluation of ARM Cortex Variants for Smart Cardiac Pacemaker Application”, The 2nd International Conference on Biomedical Engineering and Sciences (BIOENG'16), Las Vegas, NV, July 25 – 28, 2016.
- S. Erathne, P.S. Nair and E. John, "A Thermal-Aware Scheduling Algorithm for Core Migration in Multicore Processors", Journal of Low Power Electronics, pp. 103 - 111, June 2015.
- K. Hurt and E. John, "Analysis of Memory Sensitive SPEC CPU2006 Integer Benchmarks for Big Data Benchmarking" 1st Workshop on Performance Analysis of Big Data Systems (PABS - 2015), Austin, TX, Feb, 2015.
- N. Ferdous. B. Lee and E. John, "Performance Enhancement in Shared-Memory Multiprocessors Using Dynamically Classified Sharing Information" 33rd IEEE - International Performance Computing and Communications Conference (IPCCC- 2014), Austin, TX, Dec 5 - 7, 2014.
- J. Luo, K. Morales, B. K. Lee, E. John and Y. K. "Performance-Sensitivity and Performance-Similarity Based Workload Reduction," 31st IEEE International Performance Computing and Communications Conference (IEEE IPCCC), December 2012
- P. S. Nair, S. Erathne and E. John, "Probability-Based Optimal Sizing of Power-Gating Transistors in Full Adders for Reduced Leakage and High Performance", Journal of Low Power Electronics. Volume 8, Number 1, pp. 1-8, April 2012.
- S. Eratne, C. Romo, E. John, and W. Lin, "Reducing Thermal Hotspots in Multi-Core Processors Using Dynamic Core Scheduling", The 2011 International Conference on Computer Design. (CDES'11), Las Vegas, NV, 2011
- Binu. P. John, A. Agrawal, B. Steigerwald and E. John, "Impact of Operating System Behavior on Battery Life". Journal of Low Power Electronics. Volume 6, Number 1, pp. 10-17, April 2010
- D. Kudithipudi and E. John "Caches for Multimedia Workloads: Power and Energy Trade-offs", IEEE Transactions on Multimedia, Vol. 10, No. 6, pp. 1013 - 1021 October, 2008
- B. K. Lee, L. K. John and E. John, "Architectural Enhancements for Network Congestion Control Applications" IEEE Transactions on VLSI Systems, Vol. 14, No. 6, pp. 609-615, June, 2006